Senior Physical Design Engineer (Synthesis, SDC & STA)

Own synthesis for complex blocks and full chip designs on 10nm and below nodes Write, review, and debug SDC constraints, including partitioning and budgeting from top level to block level Drive static timing analysis through to signoff, including SI and noise closure Generate and implement functional and timing ECOs Develop timing scripts for clock skew analysis, critical path analysis, and IO interface timing Work closely with RTL, DFT, and PnR teams to close PPA targets Support formal verification and low power implementation Desired Candidate Profile 10+ years of experience in physical design, with deep hands on work in synthesis, SDC and STA Proven RTL to GDSII experience on 10nm or below nodes, with designs of 500k to 1M+ instances Power user of Synopsys and/or Cadence synthesis and timing tools (Design Compiler, Genus, PrimeTime, Tempus) Strong STA/PTSI and signal integrity closure skills Good knowledge of DFT scan insertion and its impact on timing Proficiency in Tcl, Perl, Python and Makefile Multiple tapeouts with signoff closure You treat a constraint file like code that deserves a proper review You can explain a violating path to a designer in terms they can act on You'd rather script a check once than eyeball a report a hundred times You stay calm when timing closure goes down to the wire You enjoy being the person the whole flow depends on getting it right early