Lead STA Engineer

Timing signoff is the final word on whether a chip is ready, and you'll be the one giving it. As the lead STA specialist, you'll set the timing methodology, guide the team through closure, and make the call on what's truly clean. You'll be the reference point for anyone who needs to understand why a path is failing and what it will take to fix it. WHAT YOU'LL DO Lead full chip and block level STA and timing signoff on advanced nodes (10nm and below) Define timing methodology, signoff criteria, corners and modes Own SI and noise analysis, OCV/AOCV/POCV strategy, and signoff closure Drive ECO generation and implementation for timing and functional fixes Review and guide constraint quality across RTL, synthesis and PnR teams Mentor and lead a team of timing engineers Build and improve timing automation and reporting flows WHAT WE'RE LOOKING FOR 10+ years of physical design experience, with a strong focus on STA and timing signoff Proven experience leading timing closure on complex SoCs at 10nm or below Expert level knowledge of PrimeTime and/or Tempus, including PTSI Deep understanding of SDC, multimode multicorner analysis and variation modelling Strong scripting in Tcl, Perl and Python Experience leading or mentoring engineers Multiple successful tapeouts as timing owner YOU'LL THRIVE HERE IF YOU You're the one people call when nobody can explain a timing report You set the standard rather than follow someone else's You enjoy growing engineers as much as closing paths You can hold a firm line on signoff quality under schedule pressure You think in corners, modes and margins without having to try