Engineering Lead

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Position Overview We are seeking a Sr. Staff Pre-Silicon Validation/Verification Lead to drive the system-level validation of interconnect solutions (PCIe, CXL, NVMe, and UCIe) for emulation and FPGA prototyping platforms. This role focuses on defining and executing robust verification and validation strategies to ensure high-quality delivery across both the protocol and system levels. The ideal candidate will combine strong hands-on technical expertise with proven leadership capabilities.

Key Responsibilities

• Lead and drive testing and verification activities for high-speed interconnect protocols and solutions (PCIe, CXL, NVMe, and UCIe)
• Architect and drive end-to-end pre-silicon verification strategies across simulation, hardware-assisted emulation, and FPGA prototyping
• Build and scale verification environments by integrating SystemC/UVM transactors, RTL monitors, BFMs, and full software stacks (bare-metal software, operating system drivers, and software layers) to enable HW/SW co-verification
• Drive system-level validation of performance, interoperability, and scalability, including the analysis of latency, bandwidth, coherency behavior, and system bottlenecks
• Own and continuously evolve the regression strategy, including test selection, coverage tracking, and failure triage, to ensure high-quality release qualification
• Design and maintain scalable CI/CD pipelines and validation infrastructure to support continuous testing and efficient execution at scale
• Ensure QA readiness through structured validation workflows, coverage closure, and alignment with customer use cases and release criteria
• Lead deep-dive debugging and root-cause analysis of complex protocol failures, RTL issues, and system bring-up in emulation environments
• Collaborate with cross-functional teams (R&D, Product Management, Product Engineering, and Application Engineering) to ensure feature readiness, technical alignment, and the timely resolution of system bottlenecks
• Mentor and guide engineers, conduct design and test plan reviews, and ensure high-quality verification sign-off

Desired Candidate Profile

Bachelor's or Master's degree in Electronics and Communications Engineering, Computer Engineering, or a related field. 8+ years of industry experience in system-level testing and verification. Solid understanding of and hands-on experience with interconnect protocols such as PCIe, CXL, NVMe, AXI, and UCIe. Hands-on experience with hardware-assisted verification platforms (e.g., Veloce, Palladium, ZeBu) or FPGA prototyping systems. Strong expertise in verification methodologies using SystemVerilog, SystemC, and HW/SW co-verification techniques. Proficiency in C/C++, with experience in bare-metal testing and validation against Linux drivers, firmware, or hypervisors. Solid understanding of CPU architectures, memory hierarchies, and system-level concepts such as IOMMU, cache coherency, and virtualization. Strong debugging skills across RTL, protocol, and system-level issues, including transaction-level analysis and HW/SW interactions. Experience building scalable validation infrastructure, including CI/CD pipelines, regression management, and test automation using Python, Bash, or similar scripting languages. Proven ability to define verification strategies, drive execution, and lead cross-functional technical initiatives. Strong leadership and ownership, with the ability to drive execution and build high-performing teams. Excellent communication and influencing skills, with the ability to collaborate effectively across cross-functional stakeholders. Strong problem-solving and prioritization skills, with the ability to manage complex requirements and perform effectively in ambiguous environments.